/*
 * Copyright (C) 2016 MediaTek Inc.
 *
 * This program is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 */

#ifndef _MTK_DEFEEMG_
#define _MTK_DEFEEMG_

#include <linux/kernel.h>

extern void __iomem *eemg_base;
#define EEMG_BASEADDR eemg_base

#define EEMG_TEMPMONCTL0		(EEMG_BASEADDR + 0x000)
#define EEMG_TEMPMONCTL1		(EEMG_BASEADDR + 0x004)
#define EEMG_TEMPMONCTL2		(EEMG_BASEADDR + 0x008)
#define EEMG_TEMPMONINT		(EEMG_BASEADDR + 0x00C)
#define EEMG_TEMPMONINTSTS		(EEMG_BASEADDR + 0x010)
#define EEMG_TEMPMONIDET0		(EEMG_BASEADDR + 0x014)
#define EEMG_TEMPMONIDET1		(EEMG_BASEADDR + 0x018)
#define EEMG_TEMPMONIDET2		(EEMG_BASEADDR + 0x01C)

#define EEMG_TEMPH2NTHRE			(EEMG_BASEADDR + 0x024)
#define EEMG_TEMPHTHRE			(EEMG_BASEADDR + 0x028)
#define EEMG_TEMPCTHRE			(EEMG_BASEADDR + 0x02C)
#define EEMG_TEMPOFFSETH			(EEMG_BASEADDR + 0x030)
#define EEMG_TEMPOFFSETL			(EEMG_BASEADDR + 0x034)
#define EEMG_TEMPMSRCTL0			(EEMG_BASEADDR + 0x038)
#define EEMG_TEMPMSRCTL1			(EEMG_BASEADDR + 0x03C)
#define EEMG_TEMPAHBPOLL			(EEMG_BASEADDR + 0x040)
#define EEMG_TEMPAHBTO			(EEMG_BASEADDR + 0x044)
#define EEMG_TEMPADCPNP0			(EEMG_BASEADDR + 0x048)
#define EEMG_TEMPADCPNP1			(EEMG_BASEADDR + 0x04C)
#define EEMG_TEMPADCPNP2			(EEMG_BASEADDR + 0x050)
#define EEMG_TEMPADCMUX			(EEMG_BASEADDR + 0x054)
#define EEMG_TEMPADCEXT			(EEMG_BASEADDR + 0x058)
#define EEMG_TEMPADCEXT1			(EEMG_BASEADDR + 0x05C)
#define EEMG_TEMPADCEN			(EEMG_BASEADDR + 0x060)
#define EEMG_TEMPPNPMUXADDR		(EEMG_BASEADDR + 0x064)
#define EEMG_TEMPADCMUXADDR		(EEMG_BASEADDR + 0x068)
#define EEMG_TEMPADCEXTADDR		(EEMG_BASEADDR + 0x06C)
#define EEMG_TEMPADCEXT1ADDR		(EEMG_BASEADDR + 0x070)
#define EEMG_TEMPADCENADDR		(EEMG_BASEADDR + 0x074)
#define EEMG_TEMPADCVALIDADDR	(EEMG_BASEADDR + 0x078)
#define EEMG_TEMPADCVOLTADDR		(EEMG_BASEADDR + 0x07C)
#define EEMG_TEMPRDCTRL			(EEMG_BASEADDR + 0x080)
#define EEMG_TEMPADCVALIDMASK	(EEMG_BASEADDR + 0x084)
#define EEMG_TEMPADCVOLTAGESHIFT (EEMG_BASEADDR + 0x088)
#define EEMG_TEMPADCWRITECTRL	(EEMG_BASEADDR + 0x08C)
#define EEMG_TEMPMSR0			(EEMG_BASEADDR + 0x090)
#define EEMG_TEMPMSR1			(EEMG_BASEADDR + 0x094)
#define EEMG_TEMPMSR2			(EEMG_BASEADDR + 0x098)

#define EEMG_TEMPIMMD0		(EEMG_BASEADDR + 0x0A0)
#define EEMG_TEMPIMMD1		(EEMG_BASEADDR + 0x0A4)
#define EEMG_TEMPIMMD2		(EEMG_BASEADDR + 0x0A8)

#define EEMG_TEMPMONIDET3	(EEMG_BASEADDR + 0x0B0)
#define EEMG_TEMPADCPNP3		(EEMG_BASEADDR + 0x0B4)
#define EEMG_TEMPMSR3		(EEMG_BASEADDR + 0x0B8)
#define EEMG_TEMPIMMD3		(EEMG_BASEADDR + 0x0BC)
#define EEMG_TEMPPROTCTL		(EEMG_BASEADDR + 0x0C0)
#define EEMG_TEMPPROTTA		(EEMG_BASEADDR + 0x0C4)
#define EEMG_TEMPPROTTB		(EEMG_BASEADDR + 0x0C8)
#define EEMG_TEMPPROTTC		(EEMG_BASEADDR + 0x0CC)

#define EEMG_TEMPSPARE0		(EEMG_BASEADDR + 0x8F0)
#define EEMG_TEMPSPARE1		(EEMG_BASEADDR + 0x8F4)
#define EEMG_TEMPSPARE2		(EEMG_BASEADDR + 0x8F8)
#define EEMG_TEMPSPARE3		(EEMG_BASEADDR + 0x8FC)

#define EEMG_DESCHAR			(EEMG_BASEADDR + 0xC00)
#define EEMG_TEMPCHAR		(EEMG_BASEADDR + 0xC04)
#define EEMG_DETCHAR			(EEMG_BASEADDR + 0xC08)
#define EEMG_AGECHAR			(EEMG_BASEADDR + 0xC0C)
#define EEMG_DCCONFIG		(EEMG_BASEADDR + 0xC10)
#define EEMG_AGECONFIG		(EEMG_BASEADDR + 0xC14)
#define EEMG_FREQPCT30		(EEMG_BASEADDR + 0xC18)
#define EEMG_FREQPCT74		(EEMG_BASEADDR + 0xC1C)
#define EEMG_LIMITVALS		(EEMG_BASEADDR + 0xC20)
#define EEMG_VBOOT		(EEMG_BASEADDR + 0xC24)
#define EEMG_DETWINDOW		(EEMG_BASEADDR + 0xC28)
#define EEMGCONFIG		(EEMG_BASEADDR + 0xC2C)
#define EEMG_TSCALCS		(EEMG_BASEADDR + 0xC30)
#define EEMG_RUNCONFIG		(EEMG_BASEADDR + 0xC34)
#define EEMGEN			(EEMG_BASEADDR + 0xC38)
#define EEMG_INIT2VALS		(EEMG_BASEADDR + 0xC3C)
#define EEMG_DCVALUES		(EEMG_BASEADDR + 0xC40)
#define EEMG_AGEVALUES		(EEMG_BASEADDR + 0xC44)
#define EEMG_VOP30		(EEMG_BASEADDR + 0xC48)
#define EEMG_VOP74		(EEMG_BASEADDR + 0xC4C)
#define TEMPG			(EEMG_BASEADDR + 0xC50)
#define EEMGINTSTS		(EEMG_BASEADDR + 0xC54)
#define EEMGINTSTSRAW		(EEMG_BASEADDR + 0xC58)
#define EEMGINTEN		(EEMG_BASEADDR + 0xC5C)

#define EEMG_CHKSHIFT		(EEMG_BASEADDR + 0xC64)

#define EEMG_VDESIGN30		(EEMG_BASEADDR + 0xC6C)
#define EEMG_VDESIGN74		(EEMG_BASEADDR + 0xC70)

#define EEMG_AGECOUNT		(EEMG_BASEADDR + 0xC7C)
#define EEMG_SMSTATE0		(EEMG_BASEADDR + 0xC80)
#define EEMG_SMSTATE1		(EEMG_BASEADDR + 0xC84)
#define EEMG_CTL0			(EEMG_BASEADDR + 0xC88)

#define EEMGCORESEL		(EEMG_BASEADDR + 0xF00)
#define EEMG_THERMINTST		(EEMG_BASEADDR + 0xF04)
#define EEMGODINTST		(EEMG_BASEADDR + 0xF08)
#define EEMG_THSTAGE0ST		(EEMG_BASEADDR + 0xF0C)
#define EEMG_THSTAGE1ST		(EEMG_BASEADDR + 0xF10)
#define EEMG_THSTAGE2ST		(EEMG_BASEADDR + 0xF14)
#define EEMG_THAHBST0		(EEMG_BASEADDR + 0xF18)
#define EEMG_THAHBST1		(EEMG_BASEADDR + 0xF1C)
#define EEMGSPARE0		(EEMG_BASEADDR + 0xF20)
#define EEMGSPARE1		(EEMG_BASEADDR + 0xF24)
#define EEMGSPARE2		(EEMG_BASEADDR + 0xF28)
#define EEMGSPARE3		(EEMG_BASEADDR + 0xF2C)
#define EEMG_THSLPEVEB		(EEMG_BASEADDR + 0xF30)
#define EEMG_THERMAL		(EEMG_BASEADDR + 0x848)

#endif
